A Novel Low Power Bitcell Design Featuring Inherent SEU Prevention and Self Correction Capabilities †

Journal of Low Power Electronics and Applications

Oron Chertkow²  Ariel Pescovsky²  Lior Atias³  Alexander Fish³  David Bol¹ 

[1] Department of Electrical and Computer Engineering, Ben-Gurion University of the Negev, Be’er Sheva 8410501, Israel; E-Mail;Department of Electrical and Computer Engineering, Ben-Gurion University of the Negev, Be’er Sheva 8410501, Israel; E-Mail:;Faculty of Engineering, Bar-Ilan University, Ramat Gan 5290002, Israel; E-Mails:

关键词: soft errors;    SEU;    critical charge;    SRAM;    low power;    low voltage;   

DOI  :  10.3390/jlpea5020130

来源: mdpi

【 摘 要 】

The pursuit of continuous scaling of electronic devices in the semiconductor industry has led to two unintended but significant outcomes: a rapid increase in susceptibility to radiation induced errors, and an overall rise in power consumption. Operating under low voltage to reduce power only aggravates radiation related reliability issues. The proposed “SEU Hardening Incorporating Extreme Low Power Bitcell Design” (SHIELD) addresses these two major concerns simultaneously. It is based on the concept of gating the conventional cross-coupled inverters while introducing a novel “cut-off” network. This creates redundant storage nodes and eliminates the internal feedback loop during radiation particle impact. The SHIELD bitcell tolerates upsets with charge deposits over 1 pC. Simulations confirm its advantages in terms of leakage power, with more than twofold lower leakage currents than previous solutions when operated at a 700 mV supply voltage in a 65 nm process. To validate the bitcell’s robustness, several test cases and special concerns, including multiple node upsets (MNU) and half-select, are examined.

【 授权许可】

CC BY   
© 2015 by the authors; licensee MDPI, Basel, Switzerland.