Impact of adjacent transistors on the SEU sensitivity of DICE flip-flop

IEICE Electronics Express

Chen Xiaowen¹  Hua Cai²  Yang Li² 

[1] College of Computer, National University of Defense Technology;School of Electronics and Information Engineering, Changchun University of Science and technology

关键词: SEU;    adjacent transistor;    DICE flip-flop;    cross section;   

DOI  :  10.1587/elex.14.20170027

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

This paper studies the impact of adjacent transistors on the SEU sensitivity of the DICE flip-flop. We compare the SEU sensitivity of the DICE flip-flop with two different layout topologies. Heavy ion experiment results indicate the separation layout topology can reduce the SEU sensitivity of the DICE flip-flop, both in SEU threshold and SEU cross section. TCAD simulation is used to investigate the mechanisms. Simulation results indicate the higher charge collection capability of adjacent transistors in the separation layout topology is the main reason to reduce the SEU sensitivity.

【 授权许可】

CC BY