Hardened Flip-Flop Optimized for Subthreshold Operation Heavy Ion Characterization of a Radiation

Journal of Low Power Electronics and Applications

Ameet Chavan¹  Praveen Palakurthi¹  Eric MacDonald¹  Joseph Neff² 

[1] University of Texas at El Paso, Electrical and Computer Engineering, El Paso, TX 79968, USA;SPAWAR System Center, Navy, San Diego, CA 92152, USA;

关键词: ultra-low voltage operation;    subthreshold;    SEU;    flip-flop;    rad-hard;   

DOI  :  10.3390/jlpea2020168

来源: mdpi

【 摘 要 】

A novel Single Event Upset (SEU) tolerant flip-flop design is proposed, which is well suited for very-low power electronics that operate in subthreshold (<Vt ≈ 500 mV). The proposed flip-flop along with a traditional (unprotected) flip-flop, a Sense-Amplifier-based Rad-hard Flip-Flop (RSAFF) and a Dual Interlocked storage Cell (DICE) flip-flop were all fabricated in MIT Lincoln Lab’s XLP 0.15 μm fully-depleted SOI CMOS technology—a process optimized for subthreshold operation. At the Cyclotron Institute at Texas A&M University, all four cells were subjected to heavy ion characterization in which the circuits were dynamically updated with alternating data and then checked for SEUs at both subthreshold (450 mV) and superthreshold (1.5 V) levels. The proposed flip-flop never failed, while the traditional and DICE designs did demonstrate faulty behavior. Simulations were conducted with the XLP process and the proposed flip-flop provided an improved energy delay product relative to the other non-faulty rad-hard flip-flop at subthreshold voltage operation. According to the XLP models operating in subthreshold at 250 mV, performance was improved by 31% and energy consumption was reduced by 27%.

【 授权许可】

CC BY   
© 2012 by the authors; licensee MDPI, Basel, Switzerland.