An improved timing monitor for deep dynamic voltage scaling system

IEICE Electronics Express

Haikun Jin²  Bo Li¹  Haolin Gu²  Xiaoqing Wu²  Yintao Guo²  Peng Cao²  Weiwei Shan² 

[1] Electrical and Computer Engineering Department, University of Maryland;National ASIC system and research engineering center, Southeast University

关键词: low power;    Dynamic voltage scaling;    integrated circuit;   

DOI  :  10.1587/elex.10.20130089

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(6)Cited-By(2)In the current Dynamic voltage scaling (DVS) integrated circuits, sufficient timing and voltage margins are typically wasted, because it is difficult to anticipate the exact amount by which the voltage or frequency should be scaled. The on-chip timing monitoring method is effective for this problem. In this paper, an improved timing monitor circuit with a fast error comparator is designed to detect and correct timing errors, and then it is used in a DVS system on 65nm CMOS technology for deep DVS. Post-layout simulation results show that the monitor performs well in different process corners with a wide voltage range and wide temperature range. Compared with the non-DVS circuit supplied by a fixed 1.2V voltage, our timing monitor based DVS system can save, on average, 33.4% dynamic power in different corners at the expense of 22.9% increased area.

【 授权许可】

Unknown