Soft N-modular redundancy: exploiting statistics for robust computation

fault tolerance;low power;algorithmic technique;signal processing;N-modular redundancy

Kim, Eric P. ; Shanbhag, Naresh R. ; Shanbhag ; Naresh R.

关键词: fault tolerance;    low power;    algorithmic technique;    signal processing;    N-modular redundancy;   

Others  :  https://www.ideals.illinois.edu/bitstream/handle/2142/14721/Kim_Eric.pdf?sequence=2&isAllowed=y

美国|英语

来源: The Illinois Digital Environment for Access to Learning and Scholarship

【 摘 要 】

Achieving energy-efficiency in nanoscale CMOS process technologies is made challenging due to the presence of process, temperature and voltage variations. In this thesis, we present soft N-modular redundancy (soft NMR) that exploits statistics of errors due to these nanoscale artifacts in order to design robust and energy-efficient systems. In contrast to conventional NMR, soft NMR employs estimation and detection techniques in the voter. Analysis of soft NMR, NMR and ANT is given to facilitate future design of systems employing such robust techniques. We also compare NMR and soft NMR in the design of an energy-e cient and robust discrete cosine transform (DCT) image coder. Simulations in a commercial 45 nm, 1:2 V, CMOS process show that soft triple-MR (TMR) provides 10improvement in robustness and 13% power savings over TMR at the same peak signal-to-noise ratio (PSNR) of 20 dB. In addition, soft dual-MR (DMR) provides a 2x improvement in robustness and a 35% power savings over TMR at the same PSNR of 20 dB. An FPGA implementation of the 2-D DCT showed that hardware emulation results match the RTL simulations.