VAST-LP: clock gating in high-level synthesis

low power;high level synthesis

Sun, Zelei ; Chen ; Deming

关键词: low power;    high level synthesis;   

Others  :  https://www.ideals.illinois.edu/bitstream/handle/2142/90970/SUN-THESIS-2016.pdf?sequence=1&isAllowed=y

美国|英语

来源: The Illinois Digital Environment for Access to Learning and Scholarship

【 摘 要 】

High-level synthesis (HLS) promises high-quality hardware with minimal develop-ment e ort. In this thesis, we evaluate the current state-of-the-art HLS engine VASTand propose a method to generate clock-gating-friendly RTL code for downstreamlogic synthesis tools. We use one-hot-key encoding method to build the state tran-sition in hardware, and we use the state registers along with main clock signal togenerate subclock signals. By analyzing the usage of each register when thenitestate machine is in di erent states, we assign the corresponding subclock signals tothe register and reduce the unnecessary toggle of the registers when they are not inuse. CHStone benchmarks in di erent application categories are used to verify thefunctionality and test the performance of the designs. The area and power data aremeasured using downstream commercial state-of-the-art tools during logic synthesis.We gain 5% to 20% dynamic power saving with -6% to 2% area increase.