Testsofa Design Details and Theory of Operation

Miller, Carl H.¹ 

[1] Pacific Northwest National Lab. (PNNL), Richland, WA (United States)

关键词: integrated circuit;    finite state machine;    pin profiling;   

DOI  :  10.2172/1314416
RP-ID  :  PNNL--25318
PID  :  OSTI ID: 1314416
Others  :  Other: 830403000

学科分类：工程和技术（综合）

美国|英语

来源: SciTech Connect

【 摘 要 】

The Testsofa is used to explore the functioning of an integrated circuit. It characterizes pin functions via pin profiling, then serves as an interface to a Boss server which creates a finite state machine (FSM) model using branch exploration. This exploration is done via a stimulus/response process, which will be explained in the Internal Logic Testing section.