Exploration of High-level Synthesis Techniques to Improve Computational Intensive VLSI Designs

High Level Synthesis;Global Interconnect;VLSI CAD;Optimization;Algorithm

Kim, Taemin ; W. Rhett Davis, Committee Member,Eric Rotenberg, Committee Member,Xun Liu, Committee Chair,James M. Tuck, Committee Member,Kim, Taemin ; W. Rhett Davis ; Committee Member ; Eric Rotenberg ; Committee Member ; Xun Liu ; Committee Chair ; James M. Tuck ; Committee Member

University:North Carolina State University

关键词: High Level Synthesis;    Global Interconnect;    VLSI CAD;    Optimization;    Algorithm;   

Others  :  https://repository.lib.ncsu.edu/bitstream/handle/1840.16/4109/etd.pdf?sequence=1&isAllowed=y

美国|英语

来源: null

【 摘 要 】

Optimization techniques during high level synthesis procedure are often preferred since design decisions at early stages of a design flow are believed to have a large impact on design quality. In this dissertation, we present three high-level synthesis schemes to improve the power, speed and reliability of deep submicron VLSI systems. Speciﬠcally, we ﬠrst describe a simultaneous register and functional unit (FU) binding algorithm. Our algorithm targets the reduction of multiplexer inputs, shortening the total length of global interconnects. In this algorithm, we introduce three graph parameters that guide our FU and register binding. They are flow dependencies, common primary inputs and common register inputs. We maximize the interconnect sharing among FUs and registers. We then present an interconnect binding algorithm during high-level synthesis for global intercon- nect reduction. Our scheme is based on the observation that not all FUs operate at all time. When idle, FUs can be reconﬠgured as pass-through logic for data transfer, reducing interconnect requirement. Our scheme not only reduces the overall length of global interconnects but also minimizes the power overhead without introducing any timing violations. Lastly, we present a register binding algorithm with the ob jective of register minimization. We have observed that not all pipelined FUs are operating at all time. Idle pipelined FUs can be used to store data temporarily, reducing stand-alone registers.