Three-dimension scheduling under multi-cycle interconnect communications

IEICE Electronics Express

Chung-Hsin Chiang¹  Shih-Hsu Huang¹  Chun-Hua Cheng¹ 

[1] Department of Electronic Engineering, Chung Yuan Christian University

关键词: Computer Aided Design;    High Level Synthesis;    Scheduling;    Clock Selection and Interconnect Delay;   

DOI  :  10.1587/elex.2.108

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(6)Cited-By(3)The three-dimension scheduling is defined as the simultaneous application of clock selection and operation scheduling. Previous three-dimension scheduling approach does not consider the interconnect delay. However, with the advent of nanometer era, the interconnect delay may take multiple clock cycles. In this paper, we use convex programming to formulate the three-dimension scheduling problem under multi-cycle interconnect communications. Benchmark data consistently show that our approach achieves the minimum latency within an acceptable run time.

【 授权许可】

Unknown