Streamroller : A Unified Compilation and Synthesis System for StreamingApplications.

Compiler;Stream Programming;Multicore;Scheduling;IBM Cell Processor;High Level Synthesis;Computer Science;Engineering;Computer Science & Engineering

Kudlur, Manjunath V.Schreiber, Robert S. ;

University of Michigan

关键词: Compiler;    Stream Programming;    Multicore;    Scheduling;    IBM Cell Processor;    High Level Synthesis;    Computer Science;    Engineering;    Computer Science & Engineering;   

Others  :  https://deepblue.lib.umich.edu/bitstream/handle/2027.42/61662/kvman_1.pdf?sequence=1&isAllowed=y

瑞士|英语

来源: The Illinois Digital Environment for Access to Learning and Scholarship

【 摘 要 】

The growing complexity of applications has increased the need for higher processing power. In the embedded domain, the convergence of audio, video, and networking on a handheld device has prompted the need for low cost, low power,and high performance implementations of these applications in the form of customhardware. In a more mainstream domain like gaming consoles, the move towards more realism in physics simulations and graphics has forced the industry towards multicore systems. Many of the applications in these domains are streaming in nature. The key challenge is to get efficient implementations of custom hardware from these applications and map these applications efficiently onto multicore architectures.This dissertation presents a unified methodology, referred to as Streamroller, that can be applied for the problem of scheduling stream programs to multicore architectures and to the problem of automatic synthesis ofcustom hardware for stream applications. Firstly, a method called stream-graph modulo scheduling is presented, which maps stream programs effectively onto a multicore architecture. Many aspects of a real system, likelimited memory and explicit DMAs are modeled in the scheduler. The scheduler is evaluated for a set of stream programs on IBM;;s Cell processor.Secondly, an automated high-level synthesis system for creating custom hardware for stream applications is presented. The template for the custom hardware is a pipeline of accelerators. The synthesis involves designing loop accelerators for individual kernels, instantiating buffers to store data passed between kernels, and linking these building blocks to form a pipeline. A unique aspect of this system is the use of multifunction accelerators, which improves cost byefficiently sharing hardware between multiple kernels.Finally, a method to improve the integer linear program formulations used in the schedulers that exploits symmetry in the solution space ispresented. Symmetry-breaking constraints are added to the formulation, and the performance of the solver is evaluated.