Novel 10-nm Gate Length MoS2 Transistor Fabricated on Si Fin Substrate

IEEE Journal of the Electron Devices Society

Kun Luo¹  Qingzhu Zhang¹  Kunpeng Jia¹  Junfeng Li¹  Tianchun Ye¹  Yu Pan¹  Zhenhua Wu¹  Jiahan Yu¹  Zhaohao Zhang¹  Wenwu Wang¹  Huaxiang Yin¹  Kailiang Huang² 

[1] Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China;University of Chinese Academy of Sciences, Beijing, China;

关键词: MoS₂ transistor;    FinFET;    Si fin;    short gate length;   

DOI  :  10.1109/JEDS.2019.2910271

来源: DOAJ

【 摘 要 】

To allow the use of molybdenum disulfide (MoS₂) in mainstream Si CMOS manufacturing processes for improved future scaling, a novel MoS₂ transistor with a 10-nm physical gate length created using a p-type doped Si fin as the back-gate electrode is presented. The fabrication technology of the ultra-small MoS₂ device shows fully process compatibility with conventional Si-FinFET process flow and it is also the first time to realize the large-scale fabrication of the arrayed MoS₂ transistors with 10-nm gate lengths. The fabricated ultrathin transistors, consisting of 10-nm gate length and 0.7-nm monolayer CVD MoS2, exhibit good switching characteristics and the average drain current on/off ratio reaches to over 10⁶. This technology provides a promising approach for future CMOS scaling with large scale new 2-D material transistors.

【 授权许可】

Unknown