Power Scalable Radio Receiver Design Based on Signal and Interference Condition

Journal of Low Power Electronics and Applications

Satyam Dwivedi¹  Bharadwaj Amrutur² 

[1] Signal Processing Lab, KTH Royal Institute of Technology, SE-100 44 Stockholm, SwedenECE Department, Indian Institute of Science, Bangalore 560 012, India;

关键词: adaptive receiver;    low power;    receiver algorithms;    packet based communication;    sampling clock;    word-length;   

DOI  :  10.3390/jlpea2040242

来源: mdpi

【 摘 要 】

A low power adaptive digital baseband architecture is presented for a low-IF receiver of IEEE 802.15.4-2006. The digital section’s sampling frequency and bit width are used as knobs to reduce the power under favorable signal and interference scenarios, thus recovering the design margins introduced to handle the worst case conditions. We show that in a 0.13 μm CMOS technology, for an adaptive digital baseband section of the receiver, power saving can be up to 85% (0.49 mW against 3.3 mW) in favorable interference and signal conditions. The proposed concepts in the design are tested using a receiver test setup where the design is hosted on a FPGA.

【 授权许可】

CC BY   
© 2012 by the authors; licensee MDPI, Basel, Switzerland.