期刊论文详细信息
IEICE Electronics Express | |
Design methodology for determining the number of stages in a cascaded time amplifier to minimize area consumption | |
Haruo Kobayashi2  Kiichi Niitsu1  Naohiro Harigai2  | |
[1] Department of Electrical Engineering and Computer Science, Graduate School of Engineering, Nagoya University;Division of Electronics and Informatics, Faculty of Science and Technology, Gunma University | |
关键词: time amplifier; CMOS; integrated circuits; design methodology; design for testability; | |
DOI : 10.1587/elex.10.20130289 | |
学科分类:电子、光学、磁材料 | |
来源: Denshi Jouhou Tsuushin Gakkai | |
【 摘 要 】
References(4)Cited-By(2)This paper describes a design methodology for determining the number of stages in a cascaded time amplifier to minimize the area consumption. The total area consumption is categorized into three parts, which allows mathematical analysis and optimization to be performed. A combination of the proposed mathematical analysis and 2D mapping can determine the number of stages to minimize the area consumption.
【 授权许可】
Unknown
【 预 览 】
Files | Size | Format | View |
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RO201911300946105ZK.pdf | 490KB | download |