Equalization in continuous and discrete time for high speed links using 65 nm technology

high speed links;signal integrity;equalization;SERDES;Continuous time linear equalizer (CTLE);Feed-forward equalizer (FFE);integrated circuits

Jain, Ankit ; Schutt-Ainé ; José

关键词: high speed links;    signal integrity;    equalization;    SERDES;    Continuous time linear equalizer (CTLE);    Feed-forward equalizer (FFE);    integrated circuits;   

Others  :  https://www.ideals.illinois.edu/bitstream/handle/2142/90516/JAIN-THESIS-2016.pdf?sequence=1&isAllowed=y

美国|英语

来源: The Illinois Digital Environment for Access to Learning and Scholarship

【 摘 要 】

With the rapid growth of technology in areas such as the internet-of-things (IOT), network infrastructure, big data, etc., there has grown a need for low power and low cost integrated solutions in order to meet the specifications of these larger scale systems. Currently, many semiconductor industries are allocating their resources to implement different communication protocols in order to meet these demands. These integrated system components are being developed on systems-on-chips (SoCs) and are an absolute necessity in many wireline applications. Every way to reduce bit error rate, while saving chip space and power consumption is being taken, and the ability to do so is essential.Throughout the past 20 years, there has also been a lot of research into designing integrated circuits (ICs) in complementary metal-oxide semiconductor technology (CMOS), especially on designing both Tx and Rx equalizers. The equalizer is a key component in insuring communication as signals that propagate through some channel will have to endure insertion loss and cross talk, where this can cause two major problems: larger rise/fall times and lower signal levels, meaning that it will be difficult to distinguish between a "0" and a "1", and there will be less time to actually sample the signal. This thesis studies two different types of equalizers: CTLE (continuous time linear equalizer) and FFE (feed-forward equalizer). The transistor-level schematics that are implemented are done using the TSMC 65 nm CMOS process with targeted data rates of 6 Gbps and 12 Gbps. Furthermore, tutorials will be provided to explain proper design and implementation of these equalizers using the Cadence Toolset. These are all compared in terms of functionality and power consumption, along with understanding the actual use cases for each. A guide for both analysis and design will be presented, and the results will further justify equalizer choices for a given application.