CACTI-IO Technical Report

Jouppi, Norman P. ; Kahng, Andrew B. ; Muralimanohar, Naveen ; Srinivas, Vaishnav

HP Development Company

关键词: IO;    Interconnect;    SERDES;    PHY;    Memory bus;    DDR;    LPDDR;   

RP-ID  :  HPL-2013-79

学科分类：计算机科学（综合）

美国|英语

来源: HP Labs

【 摘 要 】

We describe CACTI-IO, an extension to CACTI that includes power, area and timing models for the IO and PHY of the off-chip memory interface for various server and mobile configurations. CACTI-IO enables quick design space exploration of the off-chip IO along with the DRAM and cache parameters. We describe the models added to CACTI-IO that help include the off-chip impact to the tradeoffs between memory capacity, bandwidth and power. This technical report also provides three standard configurations for the input parameters (DDR3, LPDDR2, and Wide-IO) and illustrates how the models can be modified for a custom configuration. The models are validated against SPICE simulations and show that we are within 0-15% error for different configurations. We also compare with measured results.