Novel Eight-Transistor SRAM cell for write power reduction

IEICE Electronics Express

Ajay Kumar Singh¹  C.M.R. Prabhu¹ 

[1] Faculty of Engineering & Technology, Multimedia University

关键词: low power;    SRAM cell;    write/read delay;    write power;    stability and static noise margin;   

DOI  :  10.1587/elex.7.1175

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(12)Cited-By(3)This paper presents a novel 8T SRAM cell which contains two tail transistors in the pull-down path of the respective inverter to minimize the write power consumption. The simulated results show that the proposed cell consumes about 57.87% lower power and gives faster response compared to the conventional 6T SRAM cell during a write operation. To compensate the read delay and static noise margin (SNM) losses due to the two extra tail transistors in the proposed cell, we have to enlarge the width of these two tail transistors.

【 授权许可】

Unknown