Low-power reliable SRAM cell for write/read operation

IEICE Electronics Express

Ajay Kumar Singh¹  C. M. R. Prabhu¹ 

[1] Faculty of Engineering & Technology, Multimedia University

关键词: low power;    SRAM cell;    power consumption;    leakage current;    SNM and delay;   

DOI  :  10.1587/elex.11.20140913

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(10)Low power SRAM cell is a critical component in modern VLSI systems. The major portion of the power dissipation in the SRAM cell is due to large voltage swing on the bit lines during write operation. In this paper, a low-power reliable (LPR) SRAM cell is proposed for minimizing the power consumption and to enhance the performance. A new write mechanism is proposed to reduce the charging/discharging activity on the respective bit lines. The cell is simulated in terms of power, delay and static noise margin (SNM). The simulated results show that write and read power of the proposed LPR cell are reduced up to 78% and 50% at 0.7 V (in 65 nm technology) respectively compared to the 6T cell. The proposed design achieves 2.4× higher read static noise margin (SNM) than the 6T cell.

【 授权许可】

Unknown