A low power and high density cache memory based on novel SRAM cell

IEICE Electronics Express

Ali Mehrparvar²  Arash Azizi Mazreah⁴  Mohammad Noorollahi Romani¹  Mohammad Taghi Manzuri³ 

[1] Islamic Azad University, Arak Branch;Sharif University of Technology;Islamic Azad University, Science and Research Branch & Islamic Azad University

关键词: 4T SRAM cell;    6T SRAM cell;    cell area;    leakage current;    power consumption;    cache access delay;   

DOI  :  10.1587/elex.6.1084

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(7)Cited-By(1)Based on the observation that dynamic occurrence of zeros in the cache access stream and cache-resident memory values of ordinary programs exhibit a strong bias towards zero, this paper presents a novel CMOS four-transistor (4T) SRAM cell for very high density and low power cache applications. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 20% smaller than a conventional six-transistor cell using same design rules and delay access of a cache based on new 4T SRAM cell is 32% smaller than a cache based on 6T SRAM cell. Also the dynamic and static power consumption of new cell is 40% and 20% smaller than 6T SRAM cell, respectively.

【 授权许可】

Unknown