Low-power adiabatic 9T static random access memory

The Journal of Engineering

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[1] Department of Electrical, Electronic and Computer Engineering, Faculty of Engineering, Gifu University, Gifu-shi, Japan;Department of Electrical, Electronic and Systems Engineering, Faculty of Engineering and Built Environment, National University of Malaysia (UKM), Selangor, Malaysia;Graduate School of Science and Engineering, Yamagata University, Yonezawa-shi, Japan;

关键词: SRAM chips;    MOSFET;    short-circuit currents;    low-power electronics;    low-power adiabatic 9T SRAM;    data writing;    write word line signal;    short-circuit current;    NMOS switch;    cross-coupled n-type metal-oxide semiconductor;    p-type metal-oxide semiconductor transistor;    cell structure;    trapezoidal-wave pulses;    energy dissipation;    adiabatic logic principle;    low-power adiabatic static random access memory;   

DOI  :  10.1049/joe.2014.0009

来源: publisher

【 摘 要 】

In this paper, the authors propose a novel static random access memory (SRAM) that employs the adiabatic logic principle. To reduce energy dissipation, the proposed adiabatic SRAM is driven by two trapezoidal-wave pulses. The cell structure of the proposed SRAM has two high-value resistors based on a p-type metal-oxide semiconductor transistor, a cross-coupled n-type metal-oxide semiconductor (NMOS) pair and an NMOS switch to reduce the short-circuit current. The inclusion of a transmission-gate controlled by a write word line signal allows the proposed circuit to operate as an adiabatic SRAM during data writing. Simulation results show that the energy dissipation of the proposed SRAM is lower than that of a conventional adiabatic SRAM.

【 授权许可】

CC BY