We have successfully demonstrated a novel method to form a three-dimensional array of Si or Si1-xGex nanowires that are horizontally aligned to the Si substrate. Unlike previous attempts, the nanowires of desired diameters and lengths can be readily formed at desired locations on a standard Si substrate. The process has been accomplished by epitaxial growth of Si and Si1-xGex layers, conventional lithography, reactive ion etching and selective etching of Si with respect to Si1-xGex. Therefore sensors and thermoelectric devices of nanowires can be readily integrated on Si chips, and nanowires themselves can serve as the channels of MOSFETs allowing three dimensional integration of MOSFETs for increased current drive. Among the four steps of the whole process, the thesis focuses on selective etching Si over Si1-xGex. TMAH, which is an anisotropic etchant and does not contain any alkali metals, was adopted for selective etching. It has been shown that the Si vertical etch rate is at least 300 times faster than the etch rate of Si1-xGex at 73 °C. For lateral selective etching, it turned out to be crucial to align the patterns along a certain direction. When the patterns are aligned to <110> direction, are exposed f111g planes which have the lowest etch rate and the etching proceeds only until two f111g planes meet at the center of Si layer sandwiched between the top and bottom Si1-xGex layers. After this, etching continues very slowly. On the other hand, if the patterns are aligned to [100], [110] planes are exposed but etched faster than {100} planes: the desired etch rate and the selectivity to Si1-xGex nanowires can be obtained.
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