Implementation of Double Precision Floating Point Arithmetic

IEEE 754 format;power analysis;pipelining;double precision

Sudarsanam, Yasaswini ; Xun Liu, Committee Member,Rhett Davis, Committee Member,Paul Franzon, Committee Chair,Sudarsanam, Yasaswini ; Xun Liu ; Committee Member ; Rhett Davis ; Committee Member ; Paul Franzon ; Committee Chair

University:North Carolina State University

关键词: IEEE 754 format;    power analysis;    pipelining;    double precision;   

Others  :  https://repository.lib.ncsu.edu/bitstream/handle/1840.16/862/etd.pdf?sequence=1&isAllowed=y

美国|英语

来源: null

【 摘 要 】

Floating Point Arithmetic is extensively used in the field of medical imaging, biometrics, motion capture and audio applications, including broadcast, conferencing, musical instruments and professional audio. Many of these applications need to solve sparse linear systems that use fair amounts of matrix multiplication. The objective of this thesis is to implement double precision floating point cores for addition and multiplication .These cores are targeted for Field Programmable Gate Arrays because FPGAs give the designer good control over the number of I/O pins and utilization of on chip memory. FPGAs are also comparable to floating point processors in their power consumption. The multiplier and adder cores conform to the IEEE 754 standard for double precision. The design is implemented on Xilinx ISE 8.2i and has been simulated on ModelSim 6.1i.The thesis pays significant attention to the analysis of the adder and multiplier cores in terms of pipelining and area so as to maximize throughput in any manner possible. It further throws light on variations of power with pipelining.Power measurements are done using XPower provided by ISE.