Highly Efficient Design of Pipelined ParallelFFT Using Folding Transformation

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering

article

Serin Sera Paul¹  Simy M Baby² 

[1] Applied Electronics, Ilahia College of Engineering & Technology;Dept. of ECE, Ilahia College of Engineering & Technology

关键词: Fast Fourier Transform (FFT);    folding;    pipelining;    parallel processing;    register minimization;    Vedicmultiplier;    Array multiplier;    Baugh Wooley multiplier;   

来源: Research & Reviews

【 摘 要 】

This paper presents a new parallel pipelined architecture to compute Discrete Fourier Transform (DFT) using FFT architecture. This particular architecture uses folding transformation technique as well as register minimization technique for the design of FFT architecture. Novel architectures for the computation of complex and real valued fast Fourier transform are derived. Pipelining is used to reduce the power consumption. Parallel processing and pipelining exploits concurrency. Parallel processing also aids to the reduction of power consumption by reducing the supply voltage. The power consumption is reduced very effectively using the parallel architecture. This paper includes the comparative study of the speed of operation of FFT architectures using different multipliers.

【 授权许可】

Unknown