Pipelined Architecture of Multi-Band Spectral Subtraction Algorithm for Speech Enhancement

Electronics

Mohammed Bahoura¹ 

[1] Department of Engineering, Université du Québec à Rimouski, 300, allée des Ursulines, Rimouski, QC G5L 3A1, Canada;

关键词: FPGA;    hardware/software co-simulation;    pipelining;    speech enhancement;    multi-band spectral subtraction;    signal-to-noise ratio;   

DOI  :  10.3390/electronics6040073

来源: DOAJ

【 摘 要 】

In this paper, a new pipelined architecture of the multi-band spectral subtraction algorithm has been proposed for real-time speech enhancement. The proposed hardware has been implemented on field programmable gate array (FPGA) device using Xilinx system generator (XSG), high-level programming tool, and Nexys-4 development board. The multi-band algorithm has been developed to reduce the additive colored noise that does not uniformly affect the entire frequency band of useful signal. All the algorithm steps have been successfully implemented on hardware. Pipelining has been employed on this hardware architecture to increase the data throughput. Speech enhancement performances obtained by the hardware architecture are compared to those obtained by MATLAB simulation using simulated and actual noises. The resource utilization, the maximum operating frequency, and power consumption are reported for a low-cost Artix-7 FPGA device.

【 授权许可】

Unknown