6-Bit Charge Scaling DAC and SAR ADC

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering

article

Meghana Kulkarni¹  Muttappa Shingadi¹  G.H. Kulkarni² 

[1] Department of PG Studies, VLSI Design and Embedded Systems;Department of Electrical and Electronics Engineering

关键词: Switch;    DAC Logic;    CMOS;    op-amp;    CADENCE;    SAR ADC.;   

DOI  :  10.15662/ijareeie.2014.0312061

来源: Research & Reviews

【 摘 要 】

A system which processes a signal is a combination of a number of mixed signal circuits, which require both analog and digital domain functions. To change from one domain to other, analog-to-digital (A/D) and digital-to-analog (D/A) converters are used. In this work, 1.1V, 6-bit charge scaling DAC using split array is designed and simulated. This design consists of parallel array of binary weighted linear capacitors to achieve high resolution as compared to other types of DACs. A 2:1 Multiplexer is designed to act as a switch and differential amplifier is designed to amplify the convoluted inputs in charge scaling architecture. The concept of split array is employed to reduce the total area of the capacitor required for high resolution DACs. Design uses 20fF, 40fF, 80fF capacitors to build charge scaling DAC. Design of charge scaling architecture using split array is implemented in cadence 90nm technology. Further Successive approximation register (SAR) ADC is designed using the binary weighted capacitor array as its DAC for charge redistribution purpose. Design of 1.2V, 6-bit SAR ADC is implemented using cadence at 90nm CMOS process, which consumes 802.6μW.

【 授权许可】

Unknown