Switched-Capacitor Variable Gain Amplifier with Operational Amplifier Preset Technique

ETRI Journal

关键词: acquisition time;    preset technique;    op-amp;    VGA;   

Others  :  1185843
DOI  :  10.4218/etrij.09.0208.0288

【 摘 要 】

We present a novel operational amplifier preset technique for a switched-capacitor circuit to reduce the acquisition time by improving the slewing. The acquisition time of a variable gain amplifier (VGA) using the proposed technique is reduced by 30% compared with a conventional one; therefore, the power consumption of the VGA is decreased. For additional power reduction, a programmable capacitor array scheme is used in the VGA. In the 0.13 μm CMOS process, the VGA, which consists of three-stages, occupies0.33 mm² and dissipates 19.2 mW at 60 MHz with a supply voltage of 1.2 V. The gain range is 36.03 dB, which is controlled by a 10-bit control word with a gain error of ±0.68 LSB.

   

【 参考文献 】

• [1]Y.-J. Cha, S.-H. Lee, and J.-K. Lee, "Digitally-Controlled Automatic Gain Control Circuits for CMOS CCD Camera Interface," Electron Lett., vol. 35, no. 18, 1999, pp. 1909-1910.
• [2]K. Nakamura et al., "Analog Front-End Chip-Set for Mega Pixel Camcorders," IEEE Int. Solid-State Circuits Conf., 2000, pp. 190-191.
• [3]Y. Fujimoto et al., "A Low-Power Switched-Capacitor Variable Gain Amplifier," IEEE J. Solid-State Circuits, vol. 39, no.7, 2004, pp. 1213-1216.
• [4]Y.-G. Kim and J.-K. Kwon, "Multi-bit Sigma-Delta Modulator for Low Distortion and High-Speed Operation," ETRI Journal, vol. 29, no. 6, Dec. 2007, pp. 835-837.
• [5]S.-C. Lee, Y.-D. Jeon, and J.-K. Kwon, "A 9-Bit 80-MS/s CMOS Pipelined Folding A/D Converter with an Offset Canceling Technique," ETRI Journal, vol. 29, no. 3, June 2007, pp. 408-410.
• [6]S.-C. Lee et al., "A 10b 205MS/s 1mm2 90nm CMOS Pipeline ADC for Flat-Panel Display Applications," IEEE J. Solid-State Circuits, vol. 42, no. 12, 2007, pp. 2688-2695.