Design of Transposed PolyphaseDecimation Filter Using Dadda Multiplier

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering

article

M.Ramya¹  S.Jeevitha¹ 

[1] Department of ECE, Muthayammal Engineering College

关键词: Polyphase decimation filter;    Dadda Multiplier architecture;    Power dissipation;    Carrylook ahead adder;    speed.;   

DOI  :  10.15662/ijareeie.2014.0311073

来源: Research & Reviews

【 摘 要 】

Power has become a major issue in modern VLSI design. In digital signal processing systems, multiplier plays an important role but also it consumes more power and area. While using BFD multiplier for designing transposed polyphase decimation filter, it has more dynamic power dissipation which is due to the increased switching activity during multiplication and consumes a large circuit area. Also, the number of addition depends on the number of multiplicand bits which cannot be reduced. To overcome these drawbacks, Dadda multiplier is used for better performance as much as compared to existing system.

【 授权许可】

Unknown