Low Power Multiplier Design for Polyrate Filterwith Reduced Area and High Speed Design

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering

article

S. Jagadeesh¹  S. Swapanthi¹ 

[1] Department of ECE, Aditya Engineering College

关键词: Polyphase decimation filter;    Booth multiplier;    BFD Multiplier architecture;    Area;    power dissipation;    carrylook ahead adder;    speed.;   

DOI  :  10.15662/ijareeie.2014.0312067

来源: Research & Reviews

【 摘 要 】

Multi-rate Signal processing consideration pre-owned in Digital Signal processing systems carry sample rate conversion.Systems with different input and output sample ratesare used this type of technique. In multi rate signal processing applications very adequate and attractive techniques are Interpolation and Decimation. This paper come up withefficient area minimization with high speed and low power efficient VLSI architecture for polyphase decimation filter having decimation factor as three (D=3) using Booth multiplier. We also multiply signed numbers by using booth multiplier. In this algorithmthere are individualkey performance metrics those are number of slices, maximum operating frequency, number of LUT’s, input output bonds, power consumption, setup time, hold time, propagation delay between source and destinations are estimated for the filter of length nine (N=9). The power bender is diminished inpolyphase decimation filter using Boothmultiplier which preoccupieslow-power when correlated to the conventional multiplier. By using carry look-ahead adder we can improve the speed. It was noticed that the proposed design provides increase in speed, reduction in area and slight reduction in power dissipation when set side by side to conventional and BFD multiplier and low complexity.

【 授权许可】

Unknown