Efficient Area Minimization with High Speedand Low Power Multiplier Structural Designfor Multirate Filter Design

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering

article

Ch.D.Vishnupriya¹  K.Neelima¹ 

[1] Dept of Electronics & Communication Engineering, Pragati Engineering College

关键词: Polyphase decimation filter;    Booth multiplier;    BFD Multiplier architecture;    Area;    power dissipation;    carry look ahead adder;    speed.;   

DOI  :  10.15662/ijareeie.2014.0311097

来源: Research & Reviews

【 摘 要 】

In Multi-rate Signal processing studies used in Digital Signal processing systems include sample rate conversion. This technique is used for systems with different input and output sample rates. Interpolation and Decimation is very effective and popular in multi rate signal processing applications. This paper proposes a high speed, area and power efficient VLSI architecture for polyphase decimation filter with decimation factor of three (D=3) using Booth multiplier. By using booth multiplier to multiply signed numbers also. Various key performance metrics such as number of slices, maximum operating frequency, number of LUT’s, input output bonds, power consumption, setup time, hold time, propagation delay between source and destinations are estimated for the filter of length nine (N=9).The power dissipation is reduced in polyphase decimation filter using Booth multiplier which consumes low-power when compared to the conventional multiplier. The speed is improved by using carry look-ahead adder. It was observed that the proposed scheme provides increase in speed, reduction in area and slight reduction in power dissipation when compared to conventional and BFD multiplier and low complexity.

【 授权许可】

Unknown