Design of 32?32 Barrel Shifter Using VariousAdiabatic Techniques for Low PowerApplications

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering

article

Nemili Suresh Reddy¹  P. Mahesh Kannan¹ 

[1] Department of ECE, SRM University

关键词: Power clock;    DCVSL;    DCVPAL;    CPAL;    PFAL;    Power dissipation;   

来源: Research & Reviews

【 摘 要 】

Now a day’s technology enhancement is at a blistering pace. Merely VLSI has a meteoric rise due to the adoption of new techniques. Static CMOS had a limitation of deploying constant power supply. Less power dissipation is an essential attribute for any optimized design. Varying the power supply is the very thing for preventing the power dissipation. An adiabatic logic is a new technique to reduce power dissipation. Barrel shifter is an important block in any computational hardware architecture. This paper gives a detailed account of 32 bit barrel shifter design using 3 techniques namely Differential Cascode Voltage Switch Logic( DCVSL), Differential Cascode voltage Switch Pass transistor Adiabatic Logic(DCVPAL), Complementary Pass transistor Adiabatic Logic(CPAL) and Positive Feedback Adiabatic Logic( PFAL). The analysis is carried out in Tanner spice and H-Spice using 180nm technology.

【 授权许可】

Unknown