A 48 GHz Fundamental Frequency PLL with Quadrature Clock Generation for 60 GHz Transceiver

Electronics

Lianming Li¹  Dongming Wang¹  Xu Wu¹  Depeng Cheng¹  Xiaokang Niu¹  Long He² 

[1] National Mobile Communications Research Laboratory, School of Information Science and Engineering, Southeast University, Nanjing 210000, China;Purple Mountain Laboratory, Nanjing 210000, China;

关键词: phase-locked loop;    60 GHz;    voltage control oscillator;    frequency divider;    quadrature phase calibration;    CMOS;   

DOI  :  10.3390/electronics11030415

来源: DOAJ

【 摘 要 】

This paper presents a design of a 48 GHz CMOS phase-locked loop (PLL) for 60 GHz millimeter-wave (mmWave) communication systems. For the sliding intermediate frequency (sliding-IF) transceiver applications, a fundamental frequency PLL with quadrature clock generation scheme is proposed. Specifically, with an implicit capacitive-bridged shunt peaking network, a second order harmonic filtering technique is realized in the voltage control oscillator (VCO) to broaden the bandpass response, thereby avoiding the complex common-mode resonant tank calibration and improving the phase noise performance. A robust current mode logic (CML) static frequency divider topology is adopted to realize the prescaler and to generate the quadrature clock. With the capacitive-bridged shunt peaking load and robust biasing circuit, the static frequency divider locking range and high frequency performance is improved and its reliability is enhanced over the PVT corners. To improve the image suppression ratio of the transceiver, a quadrature clock phase calibration scheme is proposed and verified. Fabricated in a 65 nm CMOS process, the PLL occupies a core area of 800 μm × 950 μm. Over the frequency range of 45.2 to 52.6 GHz, the measured PLL in-band phase noise PLL is better than −90 dBc/Hz@100 KHz offset, and its jitter is less than 155 fs. Moreover, the reference spur is less than −60 dBc/Hz.

【 授权许可】

Unknown