A 0.7V 1.6mW fractional-N synthesizers for BLE RF transceiver in 40nm CMOS

IEICE Electronics Express

article

Chenfeng Li¹  Chao Chen¹  Xiaodong Su¹ 

[1] School of Electronic Science & Engineering, Southeast University;National ASIC Center, Southeast University

关键词: PLL;    low power;    frequency divider;    charge pump;   

DOI  :  10.1587/elex.19.20220348

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

This paper presents a low-power fractional-N synthesizer for BLE with a gate-switching charge pump (CP) and high-speed prescaler. To reduce the current mismatch under low supply voltage, a master-slave rail-to-rail operational trans-conductance amplifier (OTA) structure is employed to the CP; Current self-matching technique guarantees the charging current is equal to discharging current. The embedded logic gates and power switch technique are employed to true-single-phase-clock (TSPC) to reduce power consumption and improve the operating speed of the divider. Random dither is injected into the ΔΣ modulator to prolong the period of output sequence. The proposed phase-locked loop (PLL) is implemented in the 40-nm CMOS process. It achieves -85.94dBc/Hz@100kHz and -109.18dBc/Hz@1MHz in fractional-N mode while consuming 1.6mW under a 0.7V voltage supply.

【 授权许可】

CC BY