A 2.4 GHz fractional-N PLL with a low-power true single-phase clock prescaler

IEICE Electronics Express

Xiaojuan Xia¹  Xincun Ji¹  Zixuan Wang¹  Leisheng Jin¹ 

[1] Nanjing University of Posts and Telecommunications

关键词: fractional-N frequency synthesizer;    TSPC prescaler;    low power;    PLL;   

DOI  :  10.1587/elex.14.20170065

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

A 2.4 GHz fractional-N PLL implemented in 65-nm CMOS process is presented in this letter. A TSPC dual-modulus prescaler is proposed to reduce the PLL’s power consumption by merging one of the branches of the true single-phase clocked (TSPC) D flip-flops. The measured synthesizer output frequency ranges from 2.16 to 2.7 GHz, and consumes 8 mW from a 1.3 V power supply. The in-band phase noise is −98 dBc/Hz at 100 kHz offset, and −115 dBc/Hz at 1 MHz offset at a carrier frequency of 2.438 GHz. The circuit achieves the RMS jitter of 0.86 ps and figure of merit of −230 dB, with the fractional spurs below −55 dBc.

【 授权许可】

CC BY