Partially Depleted Silicon on Insulator Phase Lock Loop

Voltage Controlled Oscillator;435 MHz;Partially Depleted;Silicon on Insulator;PLL;Phase Lock Loop;Transceiver;VCO;Quadurature VCO

Pitts, Wallace Shepherd ; Griff Bilbro, Committee Member,Paul D. Franzon, Committee Chair,Kevin Gard, Committee Member,Pitts, Wallace Shepherd ; Griff Bilbro ; Committee Member ; Paul D. Franzon ; Committee Chair ; Kevin Gard ; Committee Member

University:North Carolina State University

关键词: Voltage Controlled Oscillator;    435 MHz;    Partially Depleted;    Silicon on Insulator;    PLL;    Phase Lock Loop;    Transceiver;    VCO;    Quadurature VCO;   

Others  :  https://repository.lib.ncsu.edu/bitstream/handle/1840.16/2091/etd.pdf?sequence=1&isAllowed=y

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【 摘 要 】

A 435-MHz, Digital Low-IF (1-MHz), Double Differential Phase Shift Keying (DDPSK) Transceiver circuit for space application was the motivation for engineering our low power Quadurature Phase Lock Loop (PLL). The PLL was designed to meet specifications set forth by NASA and JPL. In this thesis, you will gain knowledge of the implemented design, transistor sizes, the layout as a whole, and the calculations used for the system design. The design consists of two cross-coupled NMOS and PMOS pair analog Voltage Controlled Oscillators with a digital feed back loop.