0.5-V Frequency Dividers in Folded MCML Exploiting Forward Body Bias: Analysis and Comparison

Electronics

Gaetano Palumbo¹  Francesco Centurelli²  Giuseppe Scotti² 

[1] DIEEI (Dipartimento di Ingegneria Elettrica Elettronica e Informatica), University of Catania, 95125 Catania, Italy;DIET (Dipartimento di Ingegneria dell’Informazione, Elettronica e Telecomunicazioni), University of Rome “La Sapienza”, 00184 Roma, Italy;

关键词: current-mode logic;    MCML;    SCL;    frequency divider;    logic design;    nanometer CMOS;   

DOI  :  10.3390/electronics10121383

来源: DOAJ

【 摘 要 】

Two frequency divider architectures in the Folded MOS Current Mode Logic which allow to operate at ultra-low voltage thanks to forward body bias are presented, analyzed, and compared. The first considered architecture exploits nType and pType divide-by-two building blocks (DIV2s) without level shifters, whereas the second one is based on the cascade of nType DIV2s with input level shifter. Both the architectures have been previously proposed by the same authors with higher supply voltages, but are able to work at a supply voltage as low as 0.5 V due to the threshold lowering allowed by forward body bias. For each architecture, analytical design strategies to optimize the divider under different operation scenarios are considered and a comparison among all the treated case studies is presented. Simulation results considering a commercial 28 nm FDSOI CMOS process are reported to confirm the advantages and features of the different architectures and design strategies. The analysis show that the use of the forward body bias allows to design frequency dividers which have the best efficiency. Moreover, we have found that the frequency divider architecture based on nType and pType DIV2s without level shifter provides always better performance both in terms of speed and power consumption approaching about 17 GHz of maximum operating frequency with less than 30 $\mathsf{\mu }\mathrm{W}$ power consumption.

【 授权许可】

Unknown