Radiation Tolerant, Low Noise Phase Locked Loops in 65 nm CMOS Technology

EPJ Web of Conferences

关键词: CMOS;    PLL;    Radiation effects;    Single-Event Upsets (SEU);    Total Ionizing Dose (TID);    Jitter;   

DOI  :  10.1051/epjconf/201817001021

来源: DOAJ

【 摘 要 】

This work presents an introduction to radiation hardened Phase Locked Loops (PLLs) for nuclear and high-energy physics application. An experimental circuit has been fabricated and irradiated with Xrays up to 600 Mrad. Heavy ions with an LET between 3.2 and 69.2 MeV.cm2/mg were used to verify the SEU cross section of the devices. A Two-photon Absorption (TPA) laser facility has been used to provide detailed results on the SEU sensitivity. The presented circuit employs TMR in the digital logic and an asynchronous phase-frequency detector (PFD) is presented. The PLL has a ringand LC-oscillator to be compared experimentally. The circuit has been fabricated in a 65 nm CMOS technology.

【 授权许可】

Unknown