Fully Integrated CMOS Phased-array PLL Transmitters.

PLL;Phased Array;CMOS;Electrical Engineering;Engineering;Electrical Engineering

Li, LiZhang, Zhengya ;

University of Michigan

关键词: PLL;    Phased Array;    CMOS;    Electrical Engineering;    Engineering;    Electrical Engineering;   

Others  :  https://deepblue.lib.umich.edu/bitstream/handle/2027.42/93908/lixli_1.pdf?sequence=1&isAllowed=y

瑞士|英语

来源: The Illinois Digital Environment for Access to Learning and Scholarship

【 摘 要 】

With more advanced technology, complete phased array system can be integrated in CMOS. Integrated CMOS phased array systems offer lower cost, lower power consumption, higher reliability and the possibility of on-chip signal processing using ever cheaper digital circuitry. This opens up possibilities for new applications such as directional point-to-point wireless communication which provides high security and is less prone to jamming by interferers. Integrated phased array systems are for the most part not too different from normal single channel transceivers. The key additional component is the phase shifter. A new phased array architecture that uses digital phase locked loop (PLL) modulator to realize phase shift is developed. To achieve phase shifting capability, PLL is a natural candidate. If we combine PLL’s phase shifting and modulation capabilities then we can realize phased array system using solely PLLs. With recent breakthrough in digital PLL, a digital PLL can generate a precise and well-controlled phase shift that analog PLLs cannot. The same phase shift capabilities can be used for data modulation. With both phase shift and data modulation capabilities, we only need an array of such PLLs to realize a phased array. Compared with conventional phased arrays, PLL based phased array can achieve more precise phase shift thus more precise radiation angle. It is also more flexible, since all channels can generate independent phase shift. A fully-integrated 5.8GHz PLL modulator prototype implemented in 65nm CMOS that achieves digitally-controlled arbitrary phase generation is presented. The PLL is a Type II fractional-N PLL with a 1-bit TDC as its PFD. Digital phase setting, which operates by adding a proportional signal to the PFD output, is incorporated in the PLL. The prototype achieves an average measured phase resolution of 2.25o and phase range of more than 720o. The entire PLL and output buffer consumes 11mW. Four of such PLLs form a prototype phased array as a proof of concept.