A 3.1 to 5 GHz CMOS Transceiver for DS-UWB Systems

ETRI Journal

关键词: CMOS;    PLL;    LPF;    VGA;    mixer;    LNA;    transceiver;    DS-UWB;   

Others  :  1185530
DOI  :  10.4218/etrij.07.0106.0321

【 摘 要 】

This paper presents a direct-conversion CMOS transceiver for fully digital DS-UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase-locked loop (PLL), and a voltage controlled oscillator (VCO). A single-ended-to-differential converter is implemented in the down-conversion mixer and a differential-to-single-ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 mm2 die using standard 0.18 m CMOS technology and a 64-pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low-power, and high-speed wireless personal area network.

   

【 参考文献 】

• [1]B. Razavi et al., " A UWB CMOS Transceiver," IEEE J. Solid-State Circuits, vol. 40, no. 12, Dec. 2005, pp. 2555-2562.
• [2]S. Iida et al., "A 3.1 to 5GHz CMOs DSSS UWB Transceiver for WPANs," ISSCC Digest of Technical Paper, Feb. 2005, pp. 214-215.
• [3]S. Lo et al., "A Dual-Antenna Phased-Array UWB Transceiver in 0.18 mm CMOS," ISSCC Digest of Technical Paper, Feb. 2006, pp. 118-119.
• [4]A. Tanaka et al., "A 1.1 V 3.1-to-9.5 GHz MB-OFDM UWB Transceiver in 90 nm CMOS," ISSCC Digest of Technical Paper, Feb. 2006, pp. 120-121.
• [5]C. Sandner et al., "A WiMedia/MBOA-Compliant CMOS RF Transceiver for UWB," ISSCC Digest of Technical Paper, Feb. 2006, pp. 122-123.
• [6]E. Fujita et al., Sony CFP Document, IEEE P802.15-03/138r/2, http://grouper.ieee.org/groups/802/15/pub/2003/ May 2003.
• [7]B. Razavi, RF Microelectronics, Prentice Hall PTR, 1998.
• [8]F.J. Huang and O. Kenneth. "A 0.5 μm CMOS T/R Switch for 900 MHz Wireless Applications," IEEE JSSC, vol. 36, no. 3, Mar. 2001, pp. 486-492.
• [9]C.W. Kim et al., "An Ultra-Wideband CMOS Low Noise Amplifier for 3-5 GHz UWB System," IEEE J. Solid-State Circuits, vol. 40, 2005, pp. 544-547.
• [10]S. Andersson, C. Svensson, and O. Drugge, "Wideband LNA for a Multi-standard Wireless Receiver in 0.18 μm CMOS," Proc. ESSCIRC, Sep. 2003, pp. 655-658.
• [11]T.H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, 2nd ed., Cambridge University Press, 2004.
• [12]A.Q. Safarian and A. Yazdi, "Design and Analysis of an Ultrawide-Band Distributed CMOS Mixer," IEEE Trans. on Very Large Scale Integration Systems, vol. 13, no. 5, May 2005.
• [13]J.K. Kwon, K.D. Kim, W.C. Song, and G.H. Cho, "Wideband High Dynamic Range CMOS Variable Gain Amplifier for Low Voltage and Low Power Wireless Applications," Electron. Lett., vol. 39, 2003, pp. 759-760.
• [14]S.-G. Lee and J.-K. Choi, "Current-Reuse Bleeding Mixer," Electron. Lett., vol. 36, 2000, pp. 696-697.
• [15]H.Q. Xiao and R. Schaumann, "Very-High-Frequency Lowpass Filter Based on a CMOS Active Inductor," Proc. ISCAS, vol. 2, 2002, pp. II-1? II-4.
• [16]S. Wu and B. Razavi, "A 900-MHz/1.8-GHz CMOS Receiver for Dualband Applications," IEEE J. Solid-State Circuits, vol. 33, no. 12, Dec. 1998, pp. 2178-2185.
• [17]A. Hajimiri and T.H. Lee, "Design Issues in CMOS Differential LC Oscillators," IEEE J. Solid-State Circuits, vol. 34, no. 5, May. 1999, pp. 717-724.