CNTFET BASED NOVEL 14T ADDER CELL FOR LOW POWER COMPUTATION

ICTACT Journal on Microelectronics

卷:3

Aswatha A.R¹  Balaji Ramakrishna S¹ 

[1] Dayananda Sagar College of Engineering, India;

关键词: cntfet;    adder cell;    full adder;    low power;    pdp;   

DOI  :  10.21917/ijme.2017.0076

来源: DOAJ

【 摘 要 】

This paper focuses on the design of a 14 transistor one bit addercell designed using CNTFET 32nm Technology to address thepower and speed issues of high performance computationalsystems. The performance metrics of the proposed adder cell iscompared by benchmarking with conventional full adderdesign, Transmission gate based full adder and Shannon’sexpression based full adders using CNTFET technology. Theproposed design has lesser delay and very low powerconsumption. The design embraces Stanford 32nm planarCNTFET library model with a power supply of 1 volt and singlewalled CNT. Extensive simulation has been carried out on theadder cells considered and the parameters such as power, delayand PDP are investigated. The effect of temperature variationon the power consumption of proposed 14T adder cell is alsoobserved to examine the robustness. The simulation resultsdemonstrate that the proposed adder delivers stable outputdrivability with substantial diminution in the leakage power.

【 授权许可】

Unknown