An energy efficient full adder cell for low voltage

IEICE Electronics Express

Mehrdad Maeen²  Omid Hashemipour¹  Keivan Navi¹ 

[1] Faculty of Electrical and Computer Engineering of Shahid Beheshti University;Department of Computer Engineering, Science & Research Branch of IAU

关键词: full adder;    low power;    very large-scale integrated (VLSI) circuit;    majority function and performance analysis;   

DOI  :  10.1587/elex.6.553

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(6)Cited-By(7)This paper presents an area efficient, high-speed and ultra low power 1-bit full adder that uses only 9 transistors. It works based on majority function and MOS capacitors. Because of the simple structure of the proposed design and reduced transistor counts, a very low power full adder is realized. It also can work more reliably at ultra low supply voltage in comparison with the previous designs. The circuit being studied is optimized for energy efficiency at 0.18-µm CMOS process technology. The adder cell is compared to four standard adders based on power consumption, speed and power delay product. Intensive simulation runs on HSPICE shows that the new adder has more than 44% in power savings over conventional CMOS adder and is 10% faster.

【 授权许可】

Unknown