A signal degradation reduction method for memristor ratioed logic (MRL) gates

IEICE Electronics Express

Xiaowei Li²  Ying Wang²  Yinhe Han²  Bosheng Liu²  Zhiqiang You¹ 

[1] College of Computer Science and Electronic Engineering, Hunan University;State Key Lab of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences

关键词: full adder;    memristor ratioed logic (MRL) gate;   

DOI  :  10.1587/elex.12.20150062

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(10)This paper presents a design strategy of eliminating signal degradation for memristor ratioed logic (MRL) gates. Based on the strategy, a novel MRL-based one-bit full adder is proposed. The inverters in circuit can effectively eliminate the degradation and restore signal integrity. To evaluate the effectiveness of the proposed one-bit full adder, an eight-bit full adder is demonstrated as a study case. Compared to the previous MRL-based standard cell design, the proposed circuit can reduce 11.1% memristor cells, 22.2% CMOS transistors, 38.9% vias, 58% power. Compared to the previous MRL-based optimized design, the proposed design can reduce 11.1% memristor cells, 12.5% CMOS transistors, 98.1% power, 98.1% energy.

【 授权许可】

Unknown