Low power 18T pass transistor logic ripple carry adder

IEICE Electronics Express

Zubaida Yusoff²  Noor Ain Kamsani¹  Mohd Nizar Hamidon¹  Veeraiyah Thangasamy¹  Shaiful Jahari Hashim¹  Muhammad Faiz Bukhori³ 

[1] Faculty of Engineering, Universiti Putra Malaysia;Faculty of Engineering, Multimedia University;Department of Electrical, Electronics & Systems Engineering, Faculty of Engineering & Built Environment, Universiti Kebangsaan Malaysia

关键词: full adder;    full-swing output;    low-power;    low-delay;    power delay product (PDP);   

DOI  :  10.1587/elex.12.20150176

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(13)In this paper, a high-speed low-power 18T CMOS full adder design featuring full-swing output is proposed. The adder is designed and simulated using pass transistor logic of the 130 nm CMOS technology, at a supply voltage of 1.2 V. The obtained Power Delay Product (PDP) of its critical path is 22 × 10�?18 J, which is a marked improvement of 61% to 98% compared against those of the 28T conventional CMOS, 20T transmission gate (TGA), 16T transmission function (TFA), 14T hybrid, 24T hybrid pass logic with static CMOS, and 28T differential pass logic (DPL) full adders simulated with the same process technology. Its power consumption is lower by 32% to 85%, with speed performance comparable to those of other high-speed adders reported in the literature. Occupying an aerial footprint of only 107 µm2 (8.00 µm × 13.41 µm), the proposed full adder is also capable to function at lower supply voltages of 0.4 V and 0.8 V without significant performance degradation.

【 授权许可】

Unknown