On the design of low power 1-bit full adder cell

IEICE Electronics Express

Mehrdad Maeen²  Vahid Foroutan²  Keivan Navi¹ 

[1] Faculty of Electrical and Computer Engineering, Shahid Beheshti University, GC;Department of Computer Engineering, Science and Research Branch, Islamic Azad University

关键词: full adder;    majority function;    low power;    VLSI circuit;    performance analysis;    static CMOS inverter;    MOSCAP;   

DOI  :  10.1587/elex.6.1148

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(10)Cited-By(2)A 1-bit full adder cell based on majority function is designed and simulated. In this design the time consuming XOR gates are eliminated. Low-power consumption is targeted in implementation of our design. The circuit being studied is optimized for energy efficiency at 0.18-µm CMOS process technology. The new circuit has been compared to the previous work based on power consumption, speed and power delay product (PDP). HSPICE and Cadence simulations show that the proposed adder can work more reliably at different range of supply voltage. The proposed design has the best PDP in comparison with the others.

【 授权许可】

Unknown