Efficient Phase Unwrapping Architecture for Digital Holographic Microscopy

Sensors

Wen-Jyi Hwang¹  Shih-Chang Cheng¹ 

[1] Department of Computer Science and Information Engineering, National Taiwan Normal University, Taipei, 117, Taiwan; E-Mail:

关键词: phase unwrapping;    digital holographic microscopy;    FPGA;    reconfigurable computing;    system on programmable chip;   

DOI  :  10.3390/s111009160

来源: mdpi

【 摘 要 】

This paper presents a novel phase unwrapping architecture for accelerating the computational speed of digital holographic microscopy (DHM). A fast Fourier transform (FFT) based phase unwrapping algorithm providing a minimum squared error solution is adopted for hardware implementation because of its simplicity and robustness to noise. The proposed architecture is realized in a pipeline fashion to maximize throughput of the computation. Moreover, the number of hardware multipliers and dividers are minimized to reduce the hardware costs. The proposed architecture is used as a custom user logic in a system on programmable chip (SOPC) for physical performance measurement. Experimental results reveal that the proposed architecture is effective for expediting the computational speed while consuming low hardware resources for designing an embedded DHM system.

【 授权许可】

CC BY   
© 2011 by the authors; licensee MDPI, Basel, Switzerland.