Efficient k-Winner-Take-All Competitive Learning Hardware Architecture for On-Chip Learning

Sensors

Chien-Min Ou²  Hui-Ya Li¹ 

[1] Department of Computer Science and Information Engineering, National Taiwan Normal University, Taipei 116, Taiwan;Department of Electronic Engineering, Ching Yun University, Jhongli 320, Taiwan

关键词: reconfigurable computing;    system on programmable chip;    FPGA;    competitive learning;    k-winners-take-all;   

DOI  :  10.3390/s120911661

来源: mdpi

【 摘 要 】

A novel k-winners-take-all (k-WTA) competitive learning (CL) hardware architecture is presented for on-chip learning in this paper. The architecture is based on an efficient pipeline allowing k-WTA competition processes associated with different training vectors to be performed concurrently. The pipeline architecture employs a novel codeword swapping scheme so that neurons failing the competition for a training vector are immediately available for the competitions for the subsequent training vectors. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for realtime on-chip learning. Experimental results show that the SOPC has significantly lower training time than that of other k-WTA CL counterparts operating with or without hardware support.

【 授权许可】

CC BY   
© 2012 by the authors; licensee MDPI, Basel, Switzerland.