A Scalable Architecture For Hardware Acceleration of Large Sparse Matrix Calculations

Jacobi;Sparse;Matricies;FPGA;64-bit;Floating-Point

Hamlett, Matthew Issiah ; Dr. Paul Franzon, Committee Chair,Dr. Gianluca Lazzi, Committee Member,Dr. Michael Steer, Committee Member,Hamlett, Matthew Issiah ; Dr. Paul Franzon ; Committee Chair ; Dr. Gianluca Lazzi ; Committee Member ; Dr. Michael Steer ; Committee Member

University:North Carolina State University

关键词: Jacobi;    Sparse;    Matricies;    FPGA;    64-bit;    Floating-Point;   

Others  :  https://repository.lib.ncsu.edu/bitstream/handle/1840.16/1781/etd.pdf?sequence=1&isAllowed=y

美国|英语

来源: null

【 摘 要 】

The task of implementing the Jacobi method has been looked at from several research works over the years. The Jacobi method is considered the most ideal Iterative method for implementation on FPGAs because of its inherent parallelism and lack of data dependencies. In this work, we look specifically at solving very large matrix equations in the form of Ax = b. Here A is a sparse matrix with dimensions of 1 million x 1 million with 6 entries per row. X is the vector we are solving for, and b is a known vector. All data is in 64-bit IEEE-754 floating point format. Previous work in this area has implemented the Jacobi method using only on chip memory accesses, greatly limiting the size of the matricies that can be solved. By using external memory, we present a design that is practical and can be used to accelerate various engineering and scientific problems today. In this design, we also implement the resources necessary for Multiple FPGAs to be used in a distributive manner so as to tackle larger problems. Our design gives a peak floating point performance of 1.8 GFLOPS and a sustained floating point performance of 1.18 GFLOPS. This is a speed up factor of around 2.95 when compared to the sustained performance that is typically seen on today's general purpose computers with this type of problem. To obtain this high peak floating point performance, we present in this paper a group of memory interfaces that are capable of supplying a total data rate of 20 Gb/sec sustained.