Influence of Parasitic Capacitance on Output Voltage for Series-Connected Thin-Film Piezoelectric Devices

Sensors

Kensuke Kanda¹  Takashi Saito²  Yuki Iga²  Kohei Higuchi² 

[1] Graduate School of Engineering, University of Hyogo, 2167 Shosha, Himeji 671-2280, Japan; E-Mail:;Japan Science and Technology Agency, 8111 Open Labs, 2167 Shosha, Himeji 671-2280, Japan; E-Mails:

关键词: output-voltage enhancement;    SPICE;    parasitic capacitance;    piezoelectric thin films;    MEMS;   

DOI  :  10.3390/s121216673

来源: mdpi

【 摘 要 】

Series-connected thin film piezoelectric elements can generate large output voltages. The output voltage ideally is proportional to the number of connections. However, parasitic capacitances formed by the insulation layers and derived from peripheral circuitry degrade the output voltage. Conventional circuit models are not suitable for predicting the influence of the parasitic capacitance. Therefore we proposed the simplest model of piezoelectric elements to perform simulation program with integrated circuit emphasis (SPICE) circuit simulations). The effects of the parasitic capacitances on the thin-film Pb(Zr, Ti)O₃, (PZT) elements connected in series on a SiO₂ insulator are demonstrated. The results reveal the negative effect on the output voltage caused by the parasitic capacitances of the insulation layers. The design guidelines for the devices using series-connected piezoelectric elements are explained.

【 授权许可】

CC BY   
© 2012 by the authors; licensee MDPI, Basel, Switzerland