MNA stamping for transient circuit simulation using SPICE

MNA;Stamping;SPICE;simulation

Verma, Vishesh ; Schutt-Ainé ; José E.

关键词: MNA;    Stamping;    SPICE;    simulation;   

Others  :  https://www.ideals.illinois.edu/bitstream/handle/2142/102467/VERMA-THESIS-2018.pdf?sequence=1&isAllowed=y

美国|英语

来源: The Illinois Digital Environment for Access to Learning and Scholarship

【 摘 要 】

Simulation is an essential step in the circuit design procedure, helping to verify the behavior of a designed circuit and dramatically reducing the time and effort required for debugging a given design. However, to analyze this behavior, we require an interface between the circuit design and the computer’s computational capabilities. This translation can be done in various ways depending on what aspect of the circuit is desired to be modeled (steady-state, transient, etc.). In this thesis, we explore two of these (steady-state MNA formulation and State-Space formulation) as a first step towards transient analysis.