The Fringe-Capacitance of Etching Holes for CMOS-MEMS

Micromachines

Yi-Ta Wang²  Yuh-Chung Hu²  Wen-Chang Chu¹  Pei-Zen Chang¹ 

[1] Institute of Applied Mechanics, National Taiwan University, Taipei 10617, Taiwan;Department of Mechanical and Electromechanical Engineering, National ILan University, ILan 26041, Taiwan;

关键词: CMOS;    etching holes;    fringe capacitance;    MEMS;   

DOI  :  10.3390/mi6111445

来源: mdpi

【 摘 要 】

Movable suspended microstructures are the common feature of sensors or devices in the fields of Complementary-Metal-Oxide-Semiconductors and Micro-Electro-Mechanical Systems which are usually abbreviated as CMOS-MEMS. To suspend the microstructures, it is commonly to etch the sacrificial layer under the microstructure layer. For large-area microstructures, it is necessary to design a large number of etching holes on the microstructure to enhance the etchant uniformly and rapidly permeate into the sacrificial layer. This paper aims at evaluating the fringe capacitance caused by etching holes on microstructures and developing empirical formulas. The formula of capacitance compensation term is derived by curve-fitting on the simulation results by the commercial software ANSYS. Compared with the ANSYS simulation, the deviation of the present formula is within ±5%. The application to determine the capacitance of an electrostatic micro-beam with etching holes is demonstrated in a microstructure experiment, which agrees very well with the experimental data, and the maximum deviation is within ±8%. The present formula is with simple form, wide application range, high accuracy, and easy to use. It is expected to provide the micro-device designers to estimate the capacitance of microstructures with etching holes and predominate in the device characteristics.

【 授权许可】

CC BY   
© 2015 by the authors; licensee MDPI, Basel, Switzerland.