Fin Field Effect Transistors Performance in Analog and RF for High-k Dielectrics

Defence Science Journal

P. Vijaya Kumar¹  D. Nirmal² 

[1] Karpagam College of Engineering, Coimbatore;Karunya University, Coimbatore

关键词: CMOS;    FinFET;    Nanoscale;   

DOI  :  

学科分类：社会科学、人文和艺术（综合）

来源: Defence Scientific Information & Documentation Centre

【 摘 要 】

The high- kis needed to replaceSiO 2 as the gate dielectric to reduce the gate leakage current. The impact of a high- kgate dielectric on the device short channel performance and scalability of nanoscale double gate Fin Field Effect Transistors (FinFET) CMOS is examined by 2-D device simulations. DG FinFETs are designed with high- kat the high performance node of the 2008 Semiconductor Industry Association International Technology Roadmap for Semiconductors (ITRS). DG FinFET CMOS can be optimally designed to yield outstanding performance with good trade-offs between speed and power consumption as the gate length is scaled to < 10 nm. Using technology computer aided design (TCAD) tools a 2-D FinFET device is created and the simulations are performed on it. The optimum value of threshold voltage is identified asVT =0.653V with e=23( ZrO 2) for the 2-D device structure. For the 2-D device structure, the leakage current has been reduced to 9.47´10-14 A. High- kimproves theIon / Ioffratio of transistors for future high-speed logic applications and also improves the storage capability. Defence Science Journal, 2011, 61(3), pp.235-240 , DOI:http://dx.doi.org/10.14429/dsj.61.695

【 授权许可】

Unknown