A 3D topology based-on partial overlapped clusters for NoC

IEICE Electronics Express

Min Li³  Huaxi Gu³  Kun Wang¹  Yintang Yang² 

[1] School of Computer Science and Technology, Xidian Universtiy;School of Microelectronics, Xidian Universtiy;State Key Laboratory of ISN, Xidian University

关键词: Network-on-Chip;    3D topology;    through-silicon-via;   

DOI  :  10.1587/elex.11.20140790

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(9)Cited-By(2)Three-dimensional (3D) topology of Network-On-Chip (NoC) has become a promising way to solve the problem of IP core scale expansions. It offers greater device integration and also can provide higher-bandwidth, lower-latency and lower-consumption inter-layer communication with the help of through-silicon-vias (TSVs). However, the low yield of TSV and high overhead become a primary problems. In order to obtain better performance at relatively lower cost, this letter proposes a new 3D topology based-on Partial Overlapped Clusters (POC) for NoC, which reduces the number of routers and TSVs by sharing part of vertical links flexibly. We evaluate the proposed topology through performance analysis and simulations, the results demonstrate it can reduce the overhead distinctly and provide satisfactory performance.

【 授权许可】

Unknown